B-scan imaging example of human skin

FPGA Core for Real-Time Swept-Source OCT Engines

Overview

Swept-Source Optical Coherence Tomography (SS-OCT) allows for non-invasive, high-speed, high-resolution imaging in various biomedical or industrial applications. Particularly with optical swept sources in the longer wavelength range (e.g., 1310 nm) new imaging capabilities exist that have not been addressable with time-domain or camera-based OCT systems.

SS-OCT systems require, besides a swept source and a balanced optical receiver, fast and high-resolution data acquisition (DAQ) cards that capture the raw OCT signal. The so-called k-clock reference signal is used for the data acquisition in two possible ways:

      1. As an external clock for the ADC that captures the OCT signal at times of equidistant frequency positions

      2. It is acquired in parallel to the OCT signal on a second ADC with both ADCs being clocked internally at a fixed and
          constant frequency

The second approach is generally more robust in terms of data acquisition and is suitable to handle a greater variety of linear and nonlinear swept sources. But, it requires a fair amount of signal processing that can be accomplished in real time with a deterministic latency and reliable throughput using a DAQ card with an on-board FPGA.

Product Description

The OCT-Core receives the OCT signal and the k-clock reference signal from two ADCs along with an A-scan and B-scan trigger. For each A-scan, a remapping vector is generated from the k-clock using a Hilbert transform. This remapping vector is then used to resample the OCT signal that is equidistant in the frequency domain (k-space) before the FFT can be applied. Real-time background subtraction and dispersion compensation can be enabled. The FFT output (20.log) is stored in stored in on-board DDR memory before being streamed to the host PC through a PCI-Express interface. Raw data are available for debug purposes. Users can control the system and readout the data through hardware registers or from the provided API. A complete demo/startup system (OCT-Engine) is available as an option.

YellowSys' OCT-Core is based on a VHDL code, packaged as a blackbox with well-defined interfaces, and has been integrated for Keysight digitizers (currently type U5303A).


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YellowSys Graphical User Interface

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